With advances of semiconductor process technology and the decreasing of process node, metal gate process is widely applied to achieve ideal threshold voltage and to improve device performance. However, as the critical dimension of device further shrinks, the structure of conventional MOS field effect transistor (FET) cannot meet requirements for device performance even if the metal gate process is utilized. Thus multiple gate devices as a substitute for conventional devices are drawing wide attention.
Fin FET is a common multiple gate device. FIG. 1 illustrates a three-dimensional schematic for a conventional fin FET. As shown in FIG. 1, a fin FET includes a semiconductor substrate 10, a fin 14 formed on the substrate 10 by etching the substrate 10, a dielectric layer 11 formed on the surface of semiconductor 10 and a portion of sidewall of the fin 14, and a gate structure 12 formed across the fin 14 over the top and sidewall of the fin 14. The gate structure 12 includes a gate dielectric layer (not shown) and a gate electrode (not shown) formed on the gate dielectric layer. In such a fin FET, the top area of the fin 14 and contact area between the sidewalls of fin 14 and the gate structure 12 form channel regions (e.g., provide multiple gates) to increase the driving current to improve the device performance.
A conventional method for improving device performance of the fin FET include enhancing carrier mobility in the channel regions by adjusting stress in the channel regions using strained silicon technique. A fin FET having enhanced carrier mobility in the channel regions is formed by forming a high-k dielectric layer followed by forming a stress metal layer on the surface of the high-k dielectric layer and forming metal gate electrodes on the surface of stress metal layer. As a result, stretching or compressing of the crystal lattice in the channel regions of fin FET by the stress metal layer can enhance the carrier mobility in the channel regions.
However, the stress metal layer needs to use the high-k gate dielectric layer to stretch or compress the crystal lattice in the channel regions of the fin FET, electrical properties of the high-k gate dielectric layer can be affected. This can result in more defects formed in the high-k gate dielectric layer with increased gate leakage current and decreased gate breakdown voltage.